![]() In accordance with the invention, an integrated circuit includes a test access port (TAP) and DFT scan circuitry. The present invention is a novel method and apparatus for reducing IC tester complexity and hardware while simultaneously reducing the test circuit overhead in integrated circuits without compromising the DFT and BIST functionality. This significantly reduces tester configuration and setup costs and ensures that no pin-to-pin data interference occurs. In addition, because the scan registers are loaded via a serial TAP, test data can be input to the CUT via a single serial data line rather than by applying a tester channel (e.g., a bed-of-nails tester) to each I/O pin or test node of the CUT. This gives the designer of the IC flexibility in determining which portions of the CUT warrant special on-chip testing hardware. Scan paths may be fully integrated (meaning that a scan register is substituted for each functional register in a given data path) or isolated (meaning that the scan register is not in the normal data path). Any set of data inputs can be shifted into a given scan path and applied to the CUT, and the CUT may be allowed to execute for any controlled number of clock cycles before the output is observed. ![]() First, scan test allows a high degree of controllability and observability of signals inside the chip. ![]() Scan testing is advantageous for several reasons. ![]()
0 Comments
Leave a Reply. |
AuthorWrite something about yourself. No need to be fancy, just an overview. ArchivesCategories |